1. Field of the Invention
The present invention relates generally to the testing of semiconductor memories, and more particularly to a testing implementation suitable for built-in self-repair (BISR) memories.
2. Description of the Related Art
Integrated circuits have become key components of many consumer and commercial electronic products, often replacing discrete components and enhancing functionality. The semiconductor processing technologies that produce these integrated circuits have advanced to the point where complete systems, including memories, can be reduced to a single integrated circuit or application specific integrated circuit (ASIC) device. It is a common practice for the manufacturers of such integrated circuits to thoroughly test device functionality at the manufacturing site. Because of the increasing complexity of new designs, test development costs can account for a large percentage of the total ASIC development cost.
Before integrated circuits (or “chips”) are released for shipment by a manufacturer, the devices typically undergo a variety of testing procedures. In ASIC devices incorporating integrated memories, for example, specific tests are carried out to verify that each of the memory cells within the integrated memory array(s) is functioning properly. This testing is necessary because perfect yields are difficult to achieve. It is not uncommon for a certain percentage of unpackaged ASIC die to contain memory cells which fail testing processes, due largely to non-systemic manufacturing defects and degradation faults. Such manufacturing issues are likely to increase as process geometries continue to shrink and the density of memory cells increases.
A number of memory testing strategies have evolved. If an embedded memory is buried deeply within an ASIC, a built-in self-test (BIST) is often used by semiconductor vendors. BIST allows the memory to be tested quickly with a reasonably high degree of fault coverage, without requiring complex external test equipment and large amounts of external access circuitry. One advantage BIST has over many traditional testing methods is that with BIST, memory or logic circuitry can be tested at any time in the field. This capability offers some degree of continued fault protection. BIST refers in general to any test technique in which test vectors are generated internal to an integrated circuit or ASIC. Test vectors are sequences of signals that are applied to integrated circuitry to determine if the integrated circuitry is performing as designed. BIST can be used to test memories located anywhere on the ASIC without requiring dedicated input/output pins, and can be used to test memory or logic circuitry every time power is applied to the ASIC, thereby allowing an ASIC to be easily tested after it has been incorporated in an end product. A number of software tools exist for automatically generating BIST circuitry, including RAMBIST Builder by LSI Logic of Milpitas, Calif. Such software produces area-efficient BIST circuitry for testing memories, and reduces time-to-market and test development costs. In the BIST approach, a test pattern generator and test response analyzer are incorporated directly into the device to be tested. BIST operation is controlled by supplying an external clock and utilizing a simple commencement protocol. BIST test results are typically compressed—usually to the level of “passed” or “failed”. At the end of a typical structured BIST test, or “run”, a simple pass/fail signal is asserted, indicating whether the device passed or failed the test. Intermediate pass/fail signals may also be provided, allowing individual memory locations or group of locations to be analyzed. Unlike external testing approaches, at-speed testing with BIST is readily achieved. BIST also alleviates the need for long and convoluted test vectors and may function as a surrogate for functional testing or scan testing. Further, since the BIST structures remain active on the device, BIST can be employed at the board or system level to yield reduced system testing costs, and to reduce field diagnosis and repair costs.
In order to enhance the repair process, on-chip built-in self repair (BISR) circuitry for repairing faulty memory cells has evolved. BISR circuitry functions internal to the integrated circuit without detailed interaction with external test or repair equipment. In the BISR approach, suitable test algorithms are preferably developed and implemented in BIST or BIST-like circuitry. These test patterns may be capable of detecting stuck-at, stuck-open, and bridging faults during memory column tests, as well as memory cell faults and retention faults during memory row tests. Following execution of the test patterns, the BISR circuitry analyzes the BIST “signature” (results) and, in the event of detected faults, automatically reconfigures the defective memory utilizing redundant memory elements to replace the defective ones. A memory incorporating BISR is therefore defect-tolerant. The assignee of the present invention, LSI Logic Corporation, has addressed different methods of repairing faulty memory locations utilizing BIST and BISR circuitry. Some BISR circuits are capable of repairing the faulty memory locations by redirecting the original address locations of faulty memory lines to the mapped addressed locations of the redundant columns and rows. Options for repair include either row and column replacement when a bad bit is found in a particular row or column, or single bit replacement involving storing the addresses of bad bits in a content addressable memory. If faults are randomly distributed, single bit replacement may prove to be more space efficient. However, if faults are detected involving large areas of memory in the forms of rows or columns, replacement of entire rows or columns is preferable.
There are often problems in capturing repair information by testers based upon how the error capture mode of the tester is set up. In some testers, when a functional error is observed, the tester starts over and incrementally captures the errors. In other words, once the tester observes a first failure, it stops the functional burst, goes into an error capture mode and loops back to the beginning of the test and starts over again. Thereafter, the test pattern can have multiple loop-backs based on the size of the pattern and the number of failing vectors. If the registers of all the BISR memories are connected into one scan chain (i.e., connected serially), the error capture of the test device results in incorrect information being scanned out. In particular, once the first error is encountered, the tester restarts the pattern at the beginning, but the internal information has changed because of the sequential progression of data through the scan chain. This limitation does not allow the flare registers to be connected serially. One potential solution to this limitation is to utilize parallel load registers for each register which could be loaded, and then strobed to examine the results. This approach, however, is unacceptable since it increases the BISR gate count by nearly 15%. Another alternative is to use parallel loading of the output register; however, this can cause routing congestion if there are many BISR memories in the design. Accordingly, there is a need for a testing implementation suitable for BISR memories which addresses these and other problems.